Gate dielectrics having a high dielectric constant (“high-k”) and metal gate electrodes can be utilized by semiconductor manufacturers to improve the performance of complementary metal-oxide semiconductor (“CMOS”) transistors. High-k gate dielectrics are desirable in small feature size technologies since conventional gate dielectrics, such as SiO2, are too thin and they result in high tunneling current, as well as other problems. Further, metal gate electrodes can replace polysilicon gate electrodes, which diminish NFET and PFET transistor performance due to, for example, having a high resistance and also causing undesirable depletion of carriers at the interface between gate dielectric and channel. However, NMOS transistors require a metal gate electrode having a work function of, for example, approximately 4.1 eV while PMOS transistors require a metal gate electrode having a higher work function of, for example, approximately 5.1 eV. Thus, semiconductor manufacturers are challenged to integrate metals having different work functions and high-k gate dielectrics in a fabrication process to effectively achieve dual metal NMOS and PMOS gates.
In a conventional fabrication process for CMOS transistors utilizing metal gate electrodes and high-k gate dielectrics, a first metal layer having a suitable work function for an NMOS gate and a gate dielectric layer comprising a high-k dielectric are typically deposited over NMOS and PMOS regions of a semiconductor die substrate. Since gate electrodes for NMOS and PMOS gates require different work functions, the first metal layer would not be suitable to form PMOS gate electrodes. Also, current high-k dielectric deposition processes typically cause a high concentration of negative charge to form in the high-k dielectric layer in the PMOS region, which causes an undesirable shift in gate threshold voltage and degradation of carrier mobility. Thus, in a conventional process, different metal layers must be provided in the NMOS and PMOS regions to form respective NMOS and PMOS gate electrodes.
Thus, in the conventional fabrication process, portions of the first metal layer situated in the PMOS region of the substrate are removed and a second metal layer having a work function for the PMOS gates is deposited over the gate dielectric layer in the PMOS region. Thus, the conventional process for fabricating dual metal CMOS gates discussed above is a difficult process that requires depositing a first metal layer over NMOS and PMOS regions of a substrate, removing portions of the first metal layer in the PMOS region, and depositing a second metal layer in the PMOS region.
Thus, there is a need in the art for an effective method for integrating two metals having different work functions to form dual metal CMOS gates having a high-k gate dielectric.